/*
 * @ : Copyright (c) 2021 Phytium Information Technology, Inc. 
 *  
 * SPDX-License-Identifier: Apache-2.0.
 * 
 * @Date: 2021-08-23 16:23:55
 * @LastEditTime: 2021-08-25 18:10:03
 * @Description:  This files is for 
 * 
 * @Modify History: 
 *  Ver   Who        Date         Changes
 * ----- ------     --------    --------------------------------------
 */
#ifndef BSP_DRIVERS_ETH_F_GMAC_DESC_H
#define BSP_DRIVERS_ETH_F_GMAC_DESC_H

#ifdef __cplusplus
extern "C"
{
#endif

#include "kernel.h"
#include "ft_types.h"

/********发送描述符********/

/* TDES0 包含发送的帧状态和描述符所有权信息 */
#define GMAC_DMA_TDES0_DEFERRED                  BIT(0)
#define GMAC_DMA_TDES0_UNDERFLOW_ERROR           BIT(1)
#define GMAC_DMA_TDES0_EXCESSIVE_DEFERRAL        BIT(2)
#define GMAC_DMA_TDES0_COLLISION_COUNT_MASK      GENMASK(6, 3)
#define GMAC_DMA_TDES0_VLAN_FRAME                BIT(7)
#define GMAC_DMA_TDES0_EXCESSIVE_COLLISIONS      BIT(8)
#define GMAC_DMA_TDES0_LATE_COLLISION            BIT(9)
#define GMAC_DMA_TDES0_NO_CARRIER                BIT(10)
#define GMAC_DMA_TDES0_LOSS_CARRIER              BIT(11)
#define GMAC_DMA_TDES0_PAYLOAD_ERROR             BIT(12)
#define GMAC_DMA_TDES0_FRAME_FLUSHED             BIT(13)
#define GMAC_DMA_TDES0_JABBER_TIMEOUT            BIT(14)
#define GMAC_DMA_TDES0_ERROR_SUMMARY             BIT(15)
#define GMAC_DMA_TDES0_IP_HEADER_ERROR           BIT(16)
#define GMAC_DMA_TDES0_TIME_STAMP_STATUS         BIT(17)   /* 指示已捕获相应发送帧的时间戳 */
#define GMAC_DMA_TDES0_OWN                       BIT(31)   /* 该位表示描述符归 DMA 所有 */

/* TDES1 包含缓冲区大小和控制描述符链/环和正在传输的帧的其他位 */
#define GMAC_DMA_TDES1_BUFFER1_SIZE_MASK         GENMASK(10, 0)
#define GMAC_DMA_TDES1_BUFFER2_SIZE_MASK         GENMASK(21, 11)
#define GMAC_DMA_TDES1_BUFFER2_SIZE_SHIFT        11
#define GMAC_DMA_TDES1_TIME_STAMP_ENABLE         BIT(22)
#define GMAC_DMA_TDES1_DISABLE_PADDING           BIT(23)
#define GMAC_DMA_TDES1_SECOND_ADDRESS_CHAINED    BIT(24)
#define GMAC_DMA_TDES1_END_RING                  BIT(25)
#define GMAC_DMA_TDES1_CRC_DISABLE               BIT(26)
#define GMAC_DMA_TDES1_CHECKSUM_INSERTION_MASK   GENMASK(28, 27)
#define GMAC_DMA_TDES1_CHECKSUM_INSERTION_SHIFT  27
#define GMAC_DMA_TDES1_FIRST_SEGMENT             BIT(29)
#define GMAC_DMA_TDES1_LAST_SEGMENT              BIT(30)
#define GMAC_DMA_TDES1_INTERRUPT                 BIT(31)

/********接收描述符********/

/* RDES0 包含接收的帧状态，帧长度和描述符所有权信息 */
#define GMAC_DMA_RDES0_PAYLOAD_CSUM_ERR          BIT(0)
#define GMAC_DMA_RDES0_CRC_ERROR                 BIT(1)
#define GMAC_DMA_RDES0_DRIBBLING                 BIT(2)
#define GMAC_DMA_RDES0_MII_ERROR                 BIT(3)
#define GMAC_DMA_RDES0_RECEIVE_WATCHDOG          BIT(4)
#define GMAC_DMA_RDES0_FRAME_TYPE                BIT(5)
#define GMAC_DMA_RDES0_COLLISION                 BIT(6)
#define GMAC_DMA_RDES0_IPC_CSUM_ERROR            BIT(7)
#define GMAC_DMA_RDES0_LAST_DESCRIPTOR           BIT(8)
#define GMAC_DMA_RDES0_FIRST_DESCRIPTOR          BIT(9)
#define GMAC_DMA_RDES0_VLAN_TAG                  BIT(10)
#define GMAC_DMA_RDES0_OVERFLOW_ERROR            BIT(11)
#define GMAC_DMA_RDES0_LENGTH_ERROR              BIT(12)
#define GMAC_DMA_RDES0_SA_FILTER_FAIL            BIT(13)
#define GMAC_DMA_RDES0_DESCRIPTOR_ERROR          BIT(14)
#define GMAC_DMA_RDES0_ERROR_SUMMARY             BIT(15)
#define GMAC_DMA_RDES0_FRAME_LEN_MASK            (0x3FFF << 16) /*GENMASK(29, 16)*/
#define GMAC_DMA_RDES0_FRAME_LEN_SHIFT           16
#define GMAC_DMA_RDES0_DA_FILTER_FAIL            BIT(30)
#define GMAC_DMA_RDES0_OWN                       BIT(31)

/* RDES1 包含缓冲区大小和控制描述符链/环的其他位 */
#define GMAC_DMA_RDES1_BUFFER1_SIZE_MASK         GENMASK(10, 0)
#define GMAC_DMA_RDES1_BUFFER2_SIZE_MASK         GENMASK(21, 11)
#define GMAC_DMA_RDES1_BUFFER2_SIZE_SHIFT        11
#define GMAC_DMA_RDES1_SECOND_ADDRESS_CHAINED    BIT(24)
#define GMAC_DMA_RDES1_END_RING                  BIT(25)
#define GMAC_DMA_RDES1_DISABLE_IC                BIT(31)

/* Poll demand definitions */
#define GMAC_POLL_DATA		(0xFF)

#define GMAC_DMA_GET_RX_LEN(status)              ((GMAC_DMA_RDES0_FRAME_LEN_MASK & (status)) >> GMAC_DMA_RDES0_FRAME_LEN_SHIFT)
#define GMAC_DMA_INC_DESC(x, y)                  (x) = (((x) + 1) % y)

u32 GmacDmaResumeRecv(GmacCtrl *pCtrl);
u32 GmacDmaResumeTran(GmacCtrl *pCtrl);
u32 GmacDmaRxFrame(GmacCtrl *pCtrl);
u32 GmacDmaTransFrame(GmacCtrl *pCtrl, u32 frameLen);
void GmacDmaResumeUnderflow(GmacCtrl *pCtrl);
void GmacDmaProbe(GmacCtrl *pCtrl, boolean rx);
u32 GmacRingGetReceivedFrameIT(GmacCtrl *Gmac);

#ifdef __cplusplus
}
#endif

#endif // !